RegViz: Visualize GTDNSR Bitfield

Renesas Electronics /R7FA6M1AD /GPT328 /GTDNSR

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Interpret as GTDNSR

DSELCG=0, DSCAFBL=0, DSCBFAH=0, DSCBRAL=0, DSGTRGAF=0, DSELCE=0, DSELCA=0, DSCAFBH=0, DSELCD=0, DSCARBH=0, DSCARBL=0, DSGTRGDF=0, DSGTRGDR=0, DSGTRGCF=0, DSGTRGAR=0, DSCBFAL=0, DSGTRGBF=0, DSGTRGCR=0, DSGTRGBR=0, DSCBRAH=0, DSELCH=0, DSELCC=0, DSELCB=0, DSELCF=0

Description

General PWM Timer Down Count Source Select Register

Fields

DSGTRGAR	GTETRGA Pin Rising Input Source Counter Count Down Enable 0 (0): Disable counter count down on the rising edge of GTETRGA input 1 (1): Enable counter count down on the rising edge of GTETRGA input
DSGTRGAF	GTETRGA Pin Falling Input Source Counter Count Down Enable 0 (0): Disable counter count down on the falling edge of GTETRGA input 1 (1): Enable counter count down on the falling edge of GTETRGA input.
DSGTRGBR	GTETRGB Pin Rising Input Source Counter Count Down Enable 0 (0): Disable counter count down on the rising edge of GTETRGB input 1 (1): Enable counter count down on the rising edge of GTETRGB input.
DSGTRGBF	GTETRGB Pin Falling Input Source Counter Count Down Enable 0 (0): Disable counter count down on the falling edge of GTETRGB input 1 (1): Enable counter count down on the falling edge of GTETRGB input.
DSGTRGCR	GTETRGC Pin Rising Input Source Counter Count Down Enable 0 (0): Disable counter count down on the rising edge of GTETRGC input 1 (1): Enable counter count down on the rising edge of GTETRGC input
DSGTRGCF	GTETRGC Pin Falling Input Source Counter Count Down Enable 0 (0): Disable counter count down on the falling edge of GTETRGC input 1 (1): Enable counter count down on the falling edge of GTETRGC input.
DSGTRGDR	GTETRGD Pin Rising Input Source Counter Count Down Enable 0 (0): Disable counter count down on the rising edge of GTETRGD input 1 (1): Enable counter count down on the rising edge of GTETRGD input.
DSGTRGDF	GTETRGD Pin Falling Input Source Counter Count Down Enable 0 (0): Disable counter count down on the falling edge of GTETRGD input 1 (1): Enable counter count down on the falling edge of GTETRGD input.
DSCARBL	GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable 0 (0): Disable counter count down on the rising edge of GTIOCA input when GTIOCB input is 0 1 (1): Enable counter count down on the rising edge of GTIOCA input when GTIOCB input is 0.
DSCARBH	GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable 0 (0): Disable counter count down on the rising edge of GTIOCA input when GTIOCB input is 1 1 (1): Enable counter count down on the rising edge of GTIOCA input when GTIOCB input is 1.
DSCAFBL	GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable 0 (0): Disable counter count down on the falling edge of GTIOCA input when GTIOCB input is 0 1 (1): Enable counter count down on the falling edge of GTIOCA input when GTIOCB input is 0
DSCAFBH	GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable 0 (0): Disable counter count down on the falling edge of GTIOCA input when GTIOCB input is 1 1 (1): Enable counter count down on the falling edge of GTIOCA input when GTIOCB input is 1.
DSCBRAL	GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable 0 (0): Disable counter count down on the rising edge of GTIOCB input when GTIOCA input is 0 1 (1): Enable counter count down on the rising edge of GTIOCB input when GTIOCA input is 0.
DSCBRAH	GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable 0 (0): Disable counter count down on the rising edge of GTIOCB input when GTIOCA input is 1 1 (1): Enable counter count down on the rising edge of GTIOCB input when GTIOCA input is 1.
DSCBFAL	GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable 0 (0): Disable counter count down on the falling edge of GTIOCB input when GTIOCA input is 0 1 (1): Enable counter count down on the falling edge of GTIOCB input when GTIOCA input is 0.
DSCBFAH	GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable 0 (0): Disable counter count down on the falling edge of GTIOCB input when GTIOCA input is 1 1 (1): Enable counter count down on the falling edge of GTIOCB input when GTIOCA input is 1.
DSELCA	ELC_GPTA Event Source Counter Count Down Enable 0 (0): Disable counter count down on ELC_GPTA input 1 (1): Enable counter count down on ELC_GPTA input.
DSELCB	ELC_GPTB Event Source Counter Count Down Enable 0 (0): Disable counter count down on ELC_GPTB input 1 (1): Enable counter count down on ELC_GPTB input.
DSELCC	ELC_GPTC Event Source Counter Count Down Enable 0 (0): Disable counter count down on ELC_GPTC input 1 (1): Enable counter count down on ELC_GPTC input.
DSELCD	ELC_GPTD Event Source Counter Count Down Enable 0 (0): Disable counter count down on ELC_GPTD input 1 (1): Enable counter count down on ELC_GPTD input.
DSELCE	ELC_GPTE Event Source Counter Count Down Enable 0 (0): Disable counter count down on ELC_GPTE input 1 (1): Enable counter count down on ELC_GPTE input.
DSELCF	ELC_GPTF Event Source Counter Count Down Enable 0 (0): Disable counter count down on ELC_GPTF input 1 (1): Enable counter count down on ELC_GPTF input.
DSELCG	ELC_GPTG Event Source Counter Count Down Enable 0 (0): Disable counter count down on ELC_GPTG input 1 (1): Enable counter count down on ELC_GPTG input.
DSELCH	ELC_GPTH Event Source Counter Count Down Enable 0 (0): Disable counter count down on ELC_GPTH input 1 (1): Enable counter count down on ELC_GPTH input.
Reserved	These bits are read as 00000000. The write value should be 00000000.

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